Test and debug processor and method

ABSTRACT

A Test and debug processor that can execute JTAG scans without the involvement of an external CPU or dedicated hardware. The processor includes a JTAG-bus controller logic, a JTAG port coupled to the JTAG-bus controller logic, memory capable of storing JTAG instructions, and an instruction decoding unit capable of fetching or requesting JTAG instructions from the memory. During use, the JTAG scan functions are encoded in instructions that are natively executable by the processor hardware without software interpretation. The instructions are then stored in a memory structure, fetched and executed directly by the processor. The instruction could optionally include the end-state of the bus after the operation, information about the bit count of the data to be scanned, information about the location of the data to be sent out of the JTAG port and also the location to store the received information from the test subject. Optionally, the test processor can directly access any memory location to fetch or store test data objects. This is achieved by adding a memory-bus interface to the processor allowing it to be the memory bus master. Also the test-processor can have the ability to decode and execute arithmetic and logic operation by adding an ALU the processor. The processor can also have the ability to execute register transfer operations to execute functions such as JUMP to control the run path.

[0001] This application claims the benefit of U.S. Pat. No. 60/324,240filed on Sep. 21, 12, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention pertains to electronic devices used to test anddebug electrical circuits, more particularly, such devices that use aJoint Test Action Group (JTAG) port.

[0004] 2. Description of the Related Art

[0005] With the complexity and increase of pin-count of new computerchips and the dense assembly of these chips on circuit boards, itbecomes increasingly difficult to test and debug the circuit boardsafter being assembled. A group of leading electronic companies has jointforces and developed a standard test port to be built on every chip. Thepurpose of this test port is to allow connection to a test tool to checkthe value of each pin on the chip. Some chips add more functionality tothis test port to provide access to virtually any resource inside thechip. One example of an in situ test port is the so called “JTAG” (JointTest Action Group) test port adopted by the Institute of Electrical andElectronics Engineers, Inc, and is defined as the IEEE standard 1149.1.

[0006] A common use of a test port is to test the components of acircuit board such as memory, Flash, Input/Output chips and the on-boardCPU. The test port can also be used to test the solder joints, thefunctionality of some of the on-board chips, and to program FLASH memorychips.

[0007] Typically, the testing tool is connected to a host computer thatis used to input information and display the test results. The testingtool includes an I/O interface that connects via a port, such as SCSI,serial, parallel or Ethernet to the host computer. Typically, thetesting tool's CPU is also connected to a test-bus controller chip thatallows the tool's CPU to access the test port. When the testing tooluses a JTAG test port, a JTAG bus controller with its own chip is used.

[0008] In situations where test speed is not important, the CPU can justtoggle some I/O pins that are connected to the test port to emulate theport protocol. In another implementation the test tool can be built intoan add-on card that connects directly to the host computer'smotherboard. In such implementation, the host computer CPU can alsoserve as the test tool CPU.

[0009] During testing procedures, called a SCAN in case of JTAG, thetesting tool is used to deliver a stream of bits to the test circuit.Upon receiving the bits, the test circuit responds by sending back aresponse stream of bits. By examining the response stream of bits, thetest tool and the host software can determine the state of the testcircuit and whether, for example, there are shorts or open solder pointsin the test board.

[0010] The incoming and outgoing test bits are normally stored in themain memory of the testing tool. In a typical SCAN test, the CPU readsthe data from the main memory and then writes it to the test-buscontroller. Some test-bus controllers have an input and output FIFO thatallow the CPU to read and write larger data blocks. A DMA (Direct memoryaccess) device can be used, if the controller chip has DMA controlsignals (such as request and acknowledge). Also since the number of bitsin a SCAN test can vary from one to thousands of bits, it has to bedetermined if programming the DMA controller would take more time thenusing the CPU to write the data directly to the test-bus controller.

[0011] The CPU must wait until the test-bus controller sends theoutgoing data to the board under test. If incoming stream of data isexpected, the CPU has to read it from the test-bus controller and storeit for further analysis. Again, since the number of bits can varybetween one and thousand of bits, it has to be determined if aninterrupt scheme can be used to interrupt the CPU after the results arereceived since an interrupt overhead might take more time then waitingfor the data. Even though the results can be stored in the CPUregisters, if the results are sufficiently small (i.e. 32 bit or less),most software compilers will store the results in the main memory. TheCPU uses standard logic operations such as OR, NOT or AND to check theresults of the test. These test operations can be repeated as many timesas needed to check the functionality of the board under test. Theresults can then be sent to the host computer to be displayed to theoperator.

[0012] It should be understood that a substantial amount of time iswasted due to the relatively extensive communications between thetest-tool CPU, the memory and the test-bus controller. There are threereasons for the slow communications.

[0013] First, because the test-bus controller is connected to the mainCPU as a peripheral, the main CPU must supply the test-bus controllerwith instructions to execute a specific test. It might take the main CPUhundreds of assembly instructions to supply the test-bus controller witha test instruction (such as SCAN_IR in JTAG). Since current test-busprocessors, as shown in FIG. 1, do not offer an instruction FIFO, themain CPU usually must wait until the current instruction is completedbefore supplying the next one. One of the major difficulties of addingan instruction FIFO is the need to synchronize the instruction FIFO withthe data FIFO.

[0014] Secondly, because the test-bus controller cannot execute anylogic operations, it has to wait for the main CPU to execute theseoperations to test the incoming data from the test board. Uponexamination of the board results, the main CPU can give furtherinstructions to the test-bus controller. With the current solution, itis difficult to add an Arithmetic-Logic Unit (hereinafter known as ALU)since the data is read and written in a FIFO, which cannot be addressedreliably since the data location in the FIFO depends on the speed of themain CPU and the speed of the test-bus connected to the test board.

[0015] Thirdly, because the test-bus controller cannot directly addressand access the memory where the test data is stored, the main CPU (or aDMA channel) must act as the bridge between the test-bus controller andthe memory where the test data is stored. Since the test-bus processorhas to access different test vectors in a singe test, the CPU has tocalculate the address for each one. This task is very time consuming.The reason that the test-bus controller can not access the memorydirectly is because it does not have an address bus to address andaccess individual memory locations making it a memory-bus master.

SUMMARY OF THE INVENTION

[0016] It is an object of the present invention to provide a test anddebug processor that can execute test instructions without theinvolvement of the main CPU.

[0017] It is another object of the present invention to provide such atest and debug processor in which the instructions are fetched frommemory and executed directly by the processor.

[0018] It is a further object to provide such a test and debug processorthat includes an integrally connected ALU that is able to executearithmetic and logic functions needed for the test operations directlywithout the involvement of the main CPU.

[0019] These and other objects of the invention are met by a test anddebug processor that includes a JTAG-bus controller with a JTAG portcoupled thereto, a memory means capable of storing JTAG instructions,and an instruction encoding unit capable of fetching or requesting JTAGinstructions from the memory means. The test-bus controller may alsoinclude an optional ALU and a memory-bus controller connected to thetest-bus controller logic making it a bus master.

[0020] The difference between the current existing solution and the onepurposed here is similar to the difference between a compiled and aninterpreted code. In the prior art, the main CPU has to interpret thetest code and then supply the test controller with the test data andinstructions. In the disclosed invention, the CPU can execute the testcode natively without the need for software running on the main CPU tointerpret it.

[0021] The test and debug processor is designed to directly access anymemory location. This spares the test application a lot of time sincethe main CPU does not have to keep shuffling data back and forth fromthe memory. So in a normal case where the main CPU has to calculate theaddress of the test object to be sent out, read it in to a registerinside the CPU, read the address of the test-bus controller and thenwrite the data to the controller, the controller can directly read thedata from memory in a single cycle and send it out via the test bus. Thesame process will occur when the test processor reads the data back fromthe test board and stores it in memory. So integrating the memory accesslogic into the test-bus controller saves a lot of time normally neededto access the data objects.

[0022] When the test and debug processor includes its ownarithmetic-logic unit (ALU), the test data can be processed directlywithin the test processor without the need for an external CPU. Forexample if the test software needs to check if a bit is set in the datastream received from the test board, it can do this directly while thedata being retrieved. In the currant systems, the data has to be read bythe main CPU and then tested. Since the CPU has to execute basic comparefunctions, the ALU can range from a simple comparator to any circuitthat can execute complex arithmetic and/or logic operations.

[0023] Any of these features if integrated in the current solution willhelp increase the test speed. Combining all of these features in asingle solution adds a lot of speed to the existing solution.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a schematic of a test and debug processor found in theprior art.

[0025]FIG. 2 is a schematic of the test and debug processor disclosedherein.

DESCRIPTION OF THE PREFERRED EMBODIMENT (S)

[0026] Referring to the accompanying FIG. 2, there is shown anddescribed a test and debug processor 10 that can execute native testinstructions. The processor 10 includes a JTAG-bus controller 15 with aJTAG port 17 coupled thereto, a memory means 20 or 22 capable of storingJTAG instructions 30 and scan data 31, and an instruction encoding unit25 capable of fetching or requesting JTAG instructions from the memorymeans 20 or 22. The processor 10 may also include an optional ALU 35 anda memory-bus controller 48 connected to the JTAG-bus controller logic 15making it a bus master. For example, in the case of a JTAG, the CPU canexecute a SCAN_IR or SCAN_DR instruction directly after fetching it frommemory. An example for such an instruction would be SIR R5, R6. Thiswill let the CPU choose the SCAN_IR JTAG state and send all or part ofthe contents of register 5 (R5) to the test board. The data coming backfrom the test board will be stored in register 6 (R6). Another examplewould be scan 3 bits from the byte pointed to by register 2 and ignorethe incoming data. The bit count for the scan operation can be suppliedin the instruction, from a different register in the CPU or from mainmemory.

[0027] The instructions are fetched from a memory means such as randomaccess memory (RAM) or supplied to the CPU via a FIFO memory (oneinstruction after another). The advantage of using random access memoryis to allow the processor to jump instructions based on a testcondition. A special software compiler can be used to generate the testcode to run natively in the processor core.

[0028] This concept is different from just integrating a test-buscontroller on the same chip as the CPU as it is common with serial andEthernet interfaces. In the latter case the CPU will still have toaddress the device as an 10 device. The only benefit for integrating theCPU with the 10 port is to allow zero wait-state access to the deviceand save board space. Yet the CPU has still to access it as an IOdevice. In the case of this invention, the test-bus interface isaddressable at the instruction level, which will be encoded and executedin the core. Once the processor executes one of the test instructions(such as SCAN_IR in JTAG), the code execution can stop only if theresult of this instruction is needed for a coming instruction. If theCPU hits another instruction while the test-bus logic is busy, the CPUhas to halt until the test-bus is ready to execute a new instruction.

[0029] The CPU can directly access any memory location, with aresolution of a single bit, and send it to the test board. Also when thedata is received from the test board, it can be stored in the memorydirectly without involving the main CPU. Also the memory can be used asa way of communication between the main CPU and the test processor. Thebest implementation is to make the memory dual-ported to allow bothprocessors to access it at the same time. A portion of the memory areacan be used as a communication channel to transfer messages between thetwo CPUs. A data FIFO can be also simulated in the dual ported memoryeither via soft or hardware. From the main CPU side, the memory can beaddressed in a random way via address lines or can use a pointer toaddress a specific location. So if the main CPU needs to write a programinto the test-processor memory, it can set the initial address and thenkeeps writing to a fixed port address. The internal pointers will thenincrement/decrement to point to the current memory address. This canmake the test processor addressable as an 10 device from the main CPUside.

[0030] If the test and debug processor is also used as the main CPU, itcan be connected to an IO port (such as USB, Ethernet or PCI) to sendand receive its data directly with the PC used to display the testresults. In another implementation, the test and debug processor canhave an I/O device such as a display and a keyboard to interface withthe user.

[0031] Since the test-bus logic is connected to the processor internalbuses, it can send and receive data directly to the ALU to executearithmetic and logic operations. This saves the time used to move thedata between the test-bus controller, memory and the main CPU. Also theALU can add special logic functions needed to execute test operationsfaster. Such logic operations might be of less use in a normal CPU butare used heavily in test applications. One of such functions is theability to switch between little and big endian memory formats (16, 32,64 or 128 bit words). This is the way a CPU stores a data object that islonger then a byte. Some CPUs will store the Least Significant Byte(LSB) in a lower memory location followed by the Most Significant Byte(MSB). The big endian format will store the MSB in a lower memorylocation followed by the LSB. Some test and debug applications will needto switch between these formats while accessing memory of the boardunder test.

[0032] To demonstrate the functionality of the test and debug processor,a case is presented where the tester needs to write and verify somememory in a board under test. The tests consist of writing the pattern0x55AAAA55 to a specific memory location and then verify it. The testeris connected to the board using a JTAG interface. In order to write amemory location, the test-bus processor has first to write theinstruction register to choose the memory access data path. The writeoperation consists of sending a 1-bit instruction code (read=1/write=0),a 32-bit data word followed by a 32-bit address datum used to point tothe memory word. The 32-bit long memory address must be incremented withevery scan (+4). In a read operation, the tester has to send a dummydata word followed by the address of the word to be read. The testerwill receive the data with the next scan when it is reading the nextword (the read operation is always delayed by one word since the boardunder test must have time to access the memory).

[0033] In order to execute the writing operation, the test and debugprocessor has to do the following scans. First it must do a SCAN_IR toselect the memory access path in JTAG with an end state of PAUSE_DR. Todo so it has to send a MEM_PATH value in a SCAN_IR command. Second, thetest and debug processor will execute a SCAN_DR command with a length ofone bit to select the write command. The end state will also bePAUSE_DR. R1, R2 and R3 are 32-bit registers inside the processor undertest. The processor then will first scan R1, which contain the value0x55AAAA55 into the chain. Following that, it will scan R2, whichincludes the current memory address to be written. The end state for thelast operation will be RUN_TEST_IDLE. After this operation, the CPU willadd 4 to R2 to increment the memory address by 4 bytes and decrement R3,which contains the number of words to be written. If R3 is not zero, thecycle will be repeated with the first SCAN_DR.

[0034] In the verifying operation, the CPU will also execute the firstSCAN_IR as before. Then it will scan the command bit to choose a readoperation. Since the data field is invalid, it will be filled with 0.The processor will then send R2 as an address value. The data receivedfrom the scan will be the one for the past memory access. The processorwill compare it and report any error to the test software.

[0035] Below are the symbolic instructions that show the way to writesuch a program for the JTAG test-processor. We will assume that thenumber of accesses (test length) will be in register 7 (R7). R6 willstore the memory address to start testing from.

[0036] Memory test code for example Board: MOVE R6,R2 (R2 = Startaddress) MOVE R7,R3 (R3 = # of writes) MOVE R1,TEST_VALUE (R1 =0x55AAAA55) SIR MEM_PATH,0,4,PDR (scan 4 bits with the MEM_PATH value inthe instruction register and descard incoming data. Go to Pause_DR as anend state) REP_WRITE: (Write label) SDR 0,0,1,PDR (Scan one bit withvalue 0 for write instruction) SDR R1,0,32,PDR (Scan the data value) SDRR2,0,32,RTI (Scan the address value and go to Run_Test_Idel end state)ADD R6,4,R6 (increment memory address) DEC R3 (Decrement counter) JNZREP_WRITE MOVE R6,R2 (R2 = Start address) MOVE R7,R3 (R3 = # of writes)MOVE TEST_VALUE,R1 (R1 = 0x55AAAA55) SIRMEM_PATH,0,4,PDR (scan 4 bitswith value MEM_PATH in the instruction register. Go to Pause_DR as anend state) SDR 1,0,1,PDR (Scan one bit with value 1 for readinstruction) SDR 0,0,32,PDR (Scan a dummy data value) SDR R2,0,32,RTI(Scan the address value and go to RTI end state) ADD R2,4,R2 REP_VERIFY:(Verify label) SDR 1,0,1,PDR (Scan one bit with value 1 for readinstruction) SDR 0,R3,32,PDR (Receive the previous read value inRegister 3) SDR R2,0,32,RTI (Scan the address value for next operationand go to RTI end state) CMP R3, TEST_VALUE (Compare result with testvalue) JNE ERROR ADD R2,0x4,R2 (increment memory address) DEC R3(Decrement counter) JNZ REP_VERIFY ERROR: MOV R5, DUMP_ADDRESS (write R5with the memory address used to show the error value to the main CPU)MOV R2, (R5++) (move R2 to the memory location pointer to by R5 and INCR5) MOV R1, (R5++) (move R1 to the memory location pointer to by R5 andINC R5) STOP, E (Stop with error flag for main CPU)

[0037] As shown above, this processor saves a lot of time during thetest operation. Using a current solution, the communication overheadbetween the main CPU and the test-bus controller will dramaticallydecrease. This will decrease the execution time of such a test. Alsosince the main CPU must be synchronized with the test-bus controller, ithas to check its FIFO status and command completion status after eachcommand.

[0038] In compliance with the statute, the invention described hereinhas been described in language more or less specific as to structuralfeatures. It should be understood, however, that the invention is notlimited to the specific features shown, since the means and constructionshown, is comprised only of the preferred embodiments for putting theinvention into effect. The invention is therefore claimed in any of itsforms or modifications within the legitimate and valid scope of theamended claims, appropriately interpreted in accordance with thedoctrine of equivalents.

I claim:
 1. A test and debug processor, comprising a. a JTAG-buscontroller logic; b. a JTAG port coupled to said JTAG-bus controllerlogic; c. means to access a memory structure; and, d. an instructiondecoding unit connected to said JTAG-bus controller capable of fetchingor requesting JTAG instructions from a memory structure. 2 The test anddebug processor, as recited in claim 1, further including an ALUconnected to said instruction decoding uni.
 3. The test and debugprocessor, as recited in claim 1, further having a built-in memory buscontroller allowing it to address and access a block of memory to readand write information directly without support from external hardware.4. The test and debug processor, as recited in claim 1, furtherincluding a set of register bank to allow fast access of data.
 5. Thetest and debug processor, as recited in claim 1, wherein said decodingunit decodes JTAG instructions which include fields from the followinggroup of fields that includes the following information: a scan command,a JTAG bus end state, a bit count information, a data sourceinformation, and data destination information.
 6. The test and debugprocessor, as recited in claim 1, wherein said instruction decoding unitis capable of encoding arithmetic logic instructions.
 7. The test anddebug processor, as recited in claim 1, wherein said instructiondecoding unit is capable of executing register transfer instructions. 8.The test and debug processor, as recited in claim 1, wherein saidinstruction decoding unit is capable of executing memory transferinstructions.
 9. The test-bus processor, as recited in claim 1, furtherable of executing more then one scan instruction consecutively withoutsupport from external hardware or a CPU.
 10. A test and debug processor,comprising: a JTAG-bus controller logic; b. a JTAG port coupled to saidJTAG-bus controller logic; c. a means to access a memory structure; d.an instruction decoding unit capable of fetching or requesting JTAGinstructions from a memory structure, said instruction decoding unitdecodes JTAG instructions which include fields from the following groupof fields that includes the following information: a scan command, aJTAG bus end state, a bit count information, a data source information,and data destination information, and; e. an ALU connected to saidinstruction decoding unit capable of encoding arithmetic logicinstructions.
 11. A method of executing JTAG SCAN functions comprised ofthe following steps: a. encoding a plurality of JTAG SCAN instructionscomprising type of scan, bit count information, information of theend-state of the JTAG bus, data source information, data destinationinformation into instructions, and b. selecting a test-bus processorcomprising a JTAG bus controller logic with an instruction decoding unitconnected thereto, said instruction decoder logic capable of fetching orrequesting said encoded JTAG instructions and executing them.
 12. Amethod of testing and debugging an electrical device, comprising thefollowing steps: a. selecting a test and debug processor that includes aJTAG-bus controller logic; a JTAG port coupled to said JTAG-buscontroller, a means for accessing a memory structure capable of storingJTAG instructions, and an instruction decoding unit capable of fetchingor requesting JTAG instructions from a memory structure; b. selecting anelectrical device; c. connecting said JTAG-bus controller to saidelectrical device; and, d. operating said test processor to test ordebug said electrical device.